Definition
A circuit technology that uses complementary p-channel and n-channel MOSFETs to form logic networks with almost no steady-state DC power consumption.
What it is
CMOS uses p-channel and n-channel MOSFETs to form complementary pull-up and pull-down networks. When the input is stable, usually only one side conducts; energy is consumed mainly by charging and discharging when the output switches.
Why it emerged and what problems it solved
As the number of logic gates on a chip grows, static power consumption limits system scale and power delivery. In the steady state, the complementary structure has almost no DC path from the supply to ground, shifting most power consumption to signal transitions.
Why it matters and what it enabled
CMOS made low power consumption and high density possible together, and later became the dominant logic technology for microprocessors. It also advanced battery-powered devices, space applications, and large digital systems, although dynamic power consumption and interconnect delay still require continual optimization.
Principles and impact
Problems solved
- Reduces the power consumed by MOS logic while holding a static state.
- Improves power consumption and noise margins in portable, space, and large-scale systems.
Principles
- The pull-up and pull-down networks are complementary; usually only one conducts in the steady state.
- Input transitions cause brief charging and discharging, with output capacitance determining dynamic power consumption and speed.
Improvements
- Greatly reduces static power consumption compared with single-polarity MOS logic.
- Maintains good logic noise margins at higher levels of integration.
Significance
- Became the dominant logic technology for later microprocessors and digital systems.
- Combined growing integration density with acceptable system power consumption.
History and applications
People
Frank Wanlass、Chih-Tang Sah
Organizations
Fairchild Semiconductor、RCA Research Laboratories
Events
Complementary MOS logic was proposed in 1963、CMOS entered the low-power logic and memory markets in the 1970s
Applications
Low-power logic gates、CMOS RAM、Microprocessors and digital controllers
Limitations
- Early CMOS was slower than mainstream bipolar logic, and manufacturing complementary devices was more complex.
- Dynamic power consumption, leakage, and interconnect delay increase with scale.
Upstream and downstream relations
Upstream
Sources: 1963: Complementary MOS Circuit Configuration is Invented
Sources: 1963: Complementary MOS Circuit Configuration is Invented
Downstream
No direct downstream relations recorded